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Go to Editorial ManagerMany applications consider floating point arithmetic as a key component of the computations. Combined decimal/binary arithmetic becomes an important topic supports high speed decimal/binary applications. A new 64-bit (16×16 digit) combined decimal/binary multiplier is proposed and implemented in this work that can be used for both fused multiply add (FMA) and multiplier unit. A new partial products reduction tree is shared between decimal and binary multiplier unit. The valuation and comparison result between the proposed multiplier and the previous most recent works shows 4.66 % less delay than combined decimal/binary multiplier and 19.33 % less delay than fastest standalone decimal multiplier.
This paper presents a new design to implement DFT/IDFT using the two components of a sequence, which are even and odd component sequences to solve the complexity of complex multiplications and reduce the number of multipliers. The proposed two implementations reduce the number of real multipliers needed to compute the DFT. The first proposed design gives good results for $N 512$ as compared to conventional FFT algorithm, while the second scenario gives good results for $N 1024$ as compared to conventional FFT algorithm. The proposed design is performed directly from real and imaginary part equations of the DFT sequence $X[k]$ without additional processing.