Cover
Vol. 17 No. 1 (2017)

Published: January 31, 2017

Pages: 40-47

Original Article

Fast Combined Decimal/Binary Multiplier Based on Redundant BCD 4221-8421Digit Recoding

Mohammed Nabil 1 Fatemah K Al-Assfor 2 Mohammed A. Al-Ebadi 2
1 Electrical Engineering Department University of Basrah Basra, Iraq
2 Computer Engineering Department University of Basrah Basra, Iraq
History
  • Received: October 31, 2016
  • Available Online: January 31, 2017
DOI

https://doi.org/10.33971/bjes.17.1.6

Abstract

Many applications consider floating point arithmetic as a key component of the computations. Combined decimal/binary arithmetic becomes an important topic supports high speed decimal/binary applications. A new 64-bit (16×16 digit) combined decimal/binary multiplier is proposed and implemented in this work that can be used for both fused multiply add (FMA) and multiplier unit. A new partial products reduction tree is shared between decimal and binary multiplier unit. The valuation and comparison result between the proposed multiplier and the previous most recent works shows 4.66 % less delay than combined decimal/binary multiplier and 19.33 % less delay than fastest standalone decimal multiplier.

Keywords

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